1. Field of the Invention
The present invention relates to a dynamic random access memory and a method of testing performance of the same, and more specifically to a technique for accurately screening VRT failure in a dynamic random access memory within a short period of time.
2. Description of the Related Arts
An equivalent circuit of a memory cell in a dynamic random access memory (hereinafter referred to as DRAM) is shown in FIG. 2. In FIG. 2, reference numeral 10 denotes a switch transistor in a memory cell, namely a memory cell transistor, and a memory cell transistor 10 has four terminals of a word like 1a, a bit line 1b, a storage node 1c, and a substrate terminal 1d, and an accumulator/condenser 20. Furthermore the accumulator/condenser 20 has a capacitor upper electrode 2.
Generally the memory cell transistor 10 is an N-type MOS transistor. The memory cell transistor 10 is activated (set in the selected state) when a “high” voltage is applied to the word line 1a, and is inactivated (set in the not-selected state) when a “low” voltage is applied to the word line 1a. Operations for reading from or writing information stored in a memory cell are performed when the corresponding memory cell is in the activated state. In other words, when logic “1” is written (the operation is referred to as “write” hereinafter), a voltage corresponding to the logic “1” is applied to the bit line 1b while the “high” voltage is applied to the word line 1a connected to a gate of the memory cell transistor 10. In this state, a current flows between a drain and a source in the memory cell transistor 10, and an accumulator/condenser 20 connected to the storage node 1c is charged with a voltage for the logic “1”. When a “low” voltage is applied to the word line 1a, the memory cell transistor 10 is turned OFF, and the accumulator/condenser 20 keeps the voltage for logic “1” charged therein (this state is referred to as “pause” hereinafter). When the logic “0” is written, a voltage for the logic “0” is applied to the bit line 1b in the activated state.
When the information is read out (the operation is referred to as “read” hereinafter), an electric potential in the accumulator/condenser 20 is drawn onto the bit line 1b via a drain-source path in the memory cell transistor 10 by applying the “high” voltage to the word line 1a, and the resulting signal is detected by a sense amplifier to determine whether the voltage is for “0 ” or “1”.
In the pause state, a leakage current is generated due to a reverse bias generated in a PN junction between the storage node 1c and the substrate terminal 1d. Because the accumulated electric charge dissipates in association with lapse of time due to the leakage current, for data retention it is necessary to refresh data at a prespecified interval (an operation for repeating read and rewrite).
A leakage current generated in the pause state varies in each memory cell and accordingly data retention time also varies in each cell. Therefore, before DRAMs are shipped, it is necessary to conduct a data retention test in all cells in a chip to insure retention of data for a period of time longer than the refreshing interval. Assessment of a cell for the capability of data retention is generally carried out by a test called as the pause/refresh test.
The pause/refresh test is performed by repeating the pause and read operations by writing “1” in a memory cell to be tested in the state where the transistor is turned ON. The pause time is decided based on the refresh interval as a reference. Generally, before shipment of memory cells, the pause/refresh test is carried out once, or twice by changing the testing conditions including a voltage applying pattern to cells other than the tested memory cell at pause or pause time tPAUSE as shown in FIG. 3.
It has been considered that the data retention time is fixed to a constant value specified to the memory cell, and also that retention failure can completely be screened off by carrying out once the test for each testing condition as described above. However, it has been reported, for instance, in Non-patent documents 1 and 2, that, in some memory cells, the fluctuation of data retention time like random telegraph noise as shown in FIG. 4 occurs. The fluctuation of data retention time over time as described above is referred to as Variable Retention Time (VRT). As shown in FIG. 4, in relation to the VRT phenomenon, it is often observed that a good state in which the data retention time continues for a long period of time and a bad state in which the data retention time continues only for a short period of time occur alternately, and the fluctuation includes two states or three or more states. A period of time in which each state continues varies each time measurement is performed and the fluctuation is irregular. In a memory cell showing the VRT phenomenon, even if it is determined that the data retention time is sufficiently long because the good state is observed in the shipment test, the data retention time becomes shorted because of occurrence of the bad state after shipment, which may sometimes cause retention failure. The retention failure caused by the VRT is referred to as “VRT failure” hereinafter.
Although the VRT failure is a serious failure for a customer, a frequency of occurrence of the VRT failure is extremely low. For this reason, the technique for eliminating the VRT failure has not been established.
[Non-patent document 1] D. S. Yaney, et al. “1987 I.E.D.M Technology Digest (1987)”, 1987, pp 336-339
[Non-patent document 2] P. J. Restle, et al., “1992 I.E.D.M Technology Digest (1992)”, 1992, pp 807-810